From 59b6f52c5290521ce2bd6209759e0d055c4bdc09 Mon Sep 17 00:00:00 2001
From: Myy <myy@miouyouyou.fr>
Date: Tue, 18 Jul 2017 02:21:44 +0000
Subject: [PATCH] Define VPU services in the Rockchip 3288 DTS files

And use them in the MiQi, Tinkerboard and Firefly board.

These will be used by the external Vcodec driver.

Signed-off-by: Myy <myy@miouyouyou.fr>
---
 arch/arm/boot/dts/rk3288-firefly.dtsi |  8 +++
 arch/arm/boot/dts/rk3288-miqi.dts     |  8 +++
 arch/arm/boot/dts/rk3288-tinker.dts   |  9 ++++
 arch/arm/boot/dts/rk3288.dtsi         | 97 +++++++++++++++++++++++++++++++++++
 4 files changed, 122 insertions(+)

diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index 32dabae..13c8b42 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -612,3 +612,11 @@
 &wdt {
 	status = "okay";
 };
+
+&hevc_service {
+	status = "okay";
+};
+
+&vpu_service {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 30e93f6..c165eec 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -462,3 +462,11 @@
 &wdt {
 	status = "okay";
 };
+
+&hevc_service {
+	status = "okay";
+};
+
+&vpu_service {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3288-tinker.dts b/arch/arm/boot/dts/rk3288-tinker.dts
index f601c78..6bbc8a3 100644
--- a/arch/arm/boot/dts/rk3288-tinker.dts
+++ b/arch/arm/boot/dts/rk3288-tinker.dts
@@ -534,3 +534,12 @@
 &wdt {
 	status = "okay";
 };
+
+&hevc_service {
+	status = "okay";
+};
+
+&vpu_service {
+	status = "okay";
+};
+
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 2484f11..7f94164 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -1126,6 +1126,103 @@
 		};
 	};
 
+	vpu: video-codec@ff9a0000 {
+		compatible = "rockchip,rk3288-vpu";
+		reg = <0xff9a0000 0x800>;
+		interrupts = 
+			<GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vepu", "vdpu";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk", "hclk";
+		power-domains = <&power RK3288_PD_VIDEO>;
+		iommus = <&vpu_mmu>;
+		assigned-clocks = <&cru ACLK_VCODEC>;
+		assigned-clock-rates = <400000000>;
+		status = "disabled";
+	};
+
+	vpu_service: vpu-service@ff9a0000 {
+		compatible = "rockchip,vpu_service";
+		reg = <0xff9a0000 0x800>;
+		interrupts = 
+			<GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_enc", "irq_dec";
+		clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+		clock-names = "aclk_vcodec", "hclk_vcodec";
+		power-domains = <&power RK3288_PD_VIDEO>;
+		rockchip,grf = <&grf>;
+		resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
+		reset-names = "video_a", "video_h";
+		iommus = <&vpu_mmu>;
+		iommu_enabled = <1>;
+		dev_mode = <0>;
+		status = "disabled";
+		/* 0 means ion, 1 means drm */
+		allocator = <1>;
+	};
+
+	vpu_mmu: iommu@ff9a0800 {
+		compatible = "rockchip,iommu";
+		reg = <0xff9a0800 0x100>;
+		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "vpu_mmu";
+		power-domains = <&power RK3288_PD_VIDEO>;
+		#iommu-cells = <0>;
+	};
+
+	hevc_service: hevc-service@ff9c0000 {
+		compatible = "rockchip,hevc_service";
+		reg = <0xff9c0000 0x400>;
+		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "irq_dec";
+		clocks =
+			<&cru ACLK_HEVC>,
+			<&cru HCLK_HEVC>,
+			<&cru SCLK_HEVC_CORE>,
+			<&cru SCLK_HEVC_CABAC>;
+		clock-names =
+			"aclk_vcodec",
+			"hclk_vcodec",
+			"clk_core",
+			"clk_cabac";
+		/*
+		* The 4K hevc would also work well with 500/125/300/300,
+		* no more err irq and reset request.
+		*/
+		assigned-clocks = 
+			<&cru ACLK_HEVC>,
+			<&cru HCLK_HEVC>,
+			<&cru SCLK_HEVC_CORE>,
+			<&cru SCLK_HEVC_CABAC>;
+		assigned-clock-rates =
+			<400000000>,
+			<100000000>,
+			<300000000>,
+			<300000000>;
+
+		resets = <&cru SRST_HEVC>;
+		reset-names = "video";
+		power-domains = <&power RK3288_PD_HEVC>;
+		rockchip,grf = <&grf>;
+		dev_mode = <1>;
+		iommus = <&hevc_mmu>;
+		iommu_enabled = <1>;
+		status = "disabled";
+		/* 0 means ion, 1 means drm */
+		allocator = <1>;
+	};
+
+	hevc_mmu: iommu@ff9c0440 {
+		compatible = "rockchip,iommu";
+		reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
+		interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hevc_mmu";
+		power-domains = <&power RK3288_PD_HEVC>;
+		#iommu-cells = <0>;
+	};
+
 	gpu: mali@ffa30000 {
 		compatible = "rockchip,rk3288-mali", "arm,mali-t760", "arm,mali-midgard";
 		reg = <0xffa30000 0x10000>;
-- 
2.10.2

